x86: Support pci bus scan in the early phase

On x86, some peripherals on pci buses need to be accessed in the
early phase (eg: pci uart) with a valid pci memory/io address,
thus scan the pci bus and do the corresponding resource allocation.

Signed-off-by: Bin Meng <[email protected]>
Acked-by: Simon Glass <[email protected]>

diff --git a/arch/x86/cpu/pci.c b/arch/x86/cpu/pci.c
index 404fbb68609d9fc2c55dbffe3de86fcdc1ff52f4..1eee08b314c9ac333849245f2dd939a5eed7a3d0 100644 (file)
--- a/arch/x86/cpu/pci.c
+++ b/arch/x86/cpu/pci.c
@@ -29,6 +29,7 @@ int pci_early_init_hose(struct pci_controller **hosep)
 
        board_pci_setup_hose(hose);
        pci_setup_type1(hose);
+       hose->last_busno = pci_hose_scan(hose);
        gd->arch.hose = hose;
        *hosep = hose;